For high density DRAMs, such as in the 1 GB DRAM and larger, the storage node contact and metal contact cell (SSMC) is formed simultaneously. To fabricate such a prior art DRAM cell in a semiconductor wafer, as seen in FIG. 1, a 0.2-0.4 .mu.m depth shallow trench isolation (STI) 100, a TiSi.sub.2 gate 102 and WSi.sub.2 bitline 104 are sequentially formed. The O.sub.3 TEOS based first interlayer oxide 106 is deposited and planarized by a chemical mechanical polish (CMP) process.
Turning to FIG. 2, the next step is to form contacts simultaneously in both the cell array and the periphery area of the semiconductor wafer. The storage node contacts 108, the metal contacts 110, and the tungsten interconnection 112 are simultaneously formed by depositing a tungsten layer followed by an etching step. Subsequently, a second O.sub.3 TEOS based interlayer oxide 114 is deposited, on the semiconductor wafer. The interlayer oxide 114 atop the cell array is removed.
Referring to FIG. 3, a plurality of TiN layers 116 are formed on the plurality of storage node contacts 108. The next step is to form the storage node of the memory cell, i.e., the first conductive layer of the capacitor. Thus, the storage node 118 is formed followed by the deposition of a dielectric layer 120 of the capacitor. A TiN glue layer 122 is then formed by CVD. The glue layer 122 aids in the adherence of a second conductive layer 122. The second conductive layer 122 is a polysilicon layer formed on the cell array. Next, a plate polysilicon layer 126 is formed.
Next, referring to FIG. 4, a first silicon dioxide layer 140 is formed on the semiconductor wafer followed by the formation of a triple level metallization. The cell array silicon dioxide layer 140a above the cell array is higher than the periphery silicon dioxide layer 140b above the periphery area. Therefore, even if the first metal interconnection 142 is already formed electrically coupled to the tungsten interconnection 112, it is necessary to form a second metal interconnection 144 electrically coupled to the first metal interconnection 142. To reduce the step height between the periphery area and the cell array, it is necessary to deposit a second silicon dioxide layer 146. Then, the second metal interconnection 144 is formed on the second silicon dioxide layer 146. Because a triple level metallization is used in the semiconductor DRAM of the prior art, the topography of the semiconductor wafer is conformal.
This prior art technique has several disadvantages. Because the process of triple level metallization is essential, it is necessary to use additional masks to form the contacts of the first metal interconnection 142 and the second metal interconnection 144. Further, the alignment process when forming the first metal interconnection 142 and the second metal interconnection 144 can be difficult. Moreover, when the step height of the topography between the periphery area and the cell array is large, it is difficult to maintain the conformity of the semiconductor wafer even though the second silicon dioxide layer 146 is used.